1. Filed of the Invention
The present invention is related to an electro-migration verifying method of a semiconductor integrated circuit.
2. Description of the Related Art
In general, as factors for deteriorating reliability of semiconductor integrated circuits (LSIs), the electro-migration (EM) phenomenon is known. This electro-migration phenomenon implies that when a current flows through a wiring line, since electrons collide with atoms constituting the wiring line, the atoms are moved, and thus, an atomic array is deformed, so that a short circuit and/or a disconnection of the wiring line are conducted. Although the above-described electro-migration phenomenon itself is known since ancient times, very recently, this electro-migration phenomenon may cause a serious problem due to the following reasons: That is, since there is great progress in very narrowing process technology, semiconductor integrated circuits have been manufactured in very fine and current density has been more and more increased. As to deteriorations of the semiconductor integrated circuits caused by this electro-migration (EM) phenomenon, there are two types of deteriorations, namely, an instantaneous deterioration caused by instantaneous large currents, and a progressive deterioration caused by that currents flow therethrough for a long time. Thus, as technical ideas of simulating these deteriorations so as to verify the simulated results, electro-migration verification has been proposed.
The conventional electro-migration verification corresponds to such a method that a circuit simulation is carried out so as to calculate current density with respect to wiring lines and vias within a layout, and then, the calculated current density is compared with limit values of the current density for judgement purposes (refer to, for example, patent publication 1). Also, as circuit simulators and functions of P & R tools, the conventional electro-migration verification contains calculating functions of current density and functions of comparing/judging the calculated current density with the limit values of the current density (refer to, for instance, non-patent publication 1).    Patent Publication 1: JP-A-2005-251057    Non-patent Publication 1: US Synopsys company's tool “Hsimplus”, “AstroRail”, URL dated on Feb. 21, 2006 is URL:htto://www.synopsys.com.
Conventionally, a binary judgement has been carried out which judges whether or not current density of a specific portion within a layout exceeds a limit value of the current density; when the current density exceeds the limit value of the current density, this condition has been judged as “correction is required”; and a layout correction has been carried out after electro-migration verification has been accomplished. In a so-called “signal wiring line” such as a wiring line between a driver cell and a load cell, even if a branch is present, normally, there is only one path of a current which flows between specific two points within a wiring line. If such a wiring line is employed, then the judgement of the conventional technique has no problem.
On the other hand, very recently, while mesh structures have been used in power supply wiring lines and the like, a plurality of such current paths are present that currents flow between two specific points within wiring lines. Then, even in such a case that a specific portion of a layout is disconnected, if other current paths are not disconnected, then there are some possibilities that the layout need not be corrected. Apparently, in order to achieve high reliability, layouts must be corrected in such a manner that a circuit disconnection does not partially occur. However, in LSIs of current deep sub-micron processes, congestion degrees of wiring lines are extremely high. Accordingly, there is no question that corrections of layouts may conduct increases of semiconductor chip areas. As a consequence, in wiring lines having current paths under redundant condition such as power supply wiring lines, disconnected portions of the wiring lines are correctly judged, and correction necessities of layouts are correctly judged, so that reductions of chip areas of LSIs can be realized, and at the same time, higher reliability of wiring lines thereof can be achieved.
However, the conventional electro-migration verification has the following problems. That is, such a case that a wiring line is partially disconnected and thus current paths are changed in a half way has not been modeled in the conventional electro-migration verification. As a result, especially, as to such a wiring line that a plurality of current paths are present, the disconnected portions cannot be correctly judged, but also, necessities of layout corrections cannot be correctly judged.